RISCV

An implementation of RISCV, designed in Logisim

Published on May 30, 2020

Reading time: 0 minutes.


Designed and simulated a partial implementation of a RISC-V computer in LogiSim, and wrote assembly (RV32I) to demonstrate it. To ensure the system behaved as expected, implented tests within LogiSim to assert the correct output. The project can be exported and ran on an FPGA.

Top layer of the processor